1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, in particular, to a highly sensitive receiver circuit with improved noise immunity. A preferred embodiment of the input receiver implements IEEE 802.3 10Base-T Ethernet receiver requirements utilizing a unique pulse width timer design.
2. Discussion of the Prior Art
The IEEE 802.3 standard for 10Base-T Ethernet networks specifies a receiver filtering requirement for incoming data signals. According to the standard, the receiver must reject all signals that are not within the 2-15 MHz frequency range as well as all sine waves of single cycle duration. In addition, the receiver must be capable of recognizing the 200 ns Ethernet active-to-idle transition pulse as an End-of-Packet symbol, thereby terminating reception.
Conventional bandpass filters are not suitable for 10Base-T receiver applications because they do not reject single cycle data nor are they sensitive to the End-of-Packet pulse. In addition, bandpass filters are not amplitude-sensitive.
Therefore, it is necessary that a new receiver circuit be provided to meet 802.3 10Base-T Ethernet requirements.